1. Field of the Invention
The present invention relates to capacitors within devices of semiconductor chips, and more particularly, to the formation of capacitors within a semiconductor device.
2. Description of the Related Art
Today's semiconductor devices are continually being pushed to meet stricter demands. As devices using this technology inundate the marketplace, consumers place higher demands on them. These demands include smaller, more compact devices with greater functionality.
For instance, some semiconductor applications require the integration of both digital circuitry and radio frequency (RF) circuitry in the same chip. To accomplish this, it is necessary to fabricate very specific capacitive structures. Such applications include, for example, cellular phones, portable communication devices, and other electronic devices that implement both digital and RF circuitry. In specific applications, the capacitive structures are used in RF signal processing to eliminate both low frequency components as well as direct current (DC) components from an RF signal. To date, semiconductor manufacturers have been forced to fabricate capacitors from portions of metallization lines.
The separate metallization line was required to form the individual plates necessary for a capacitor. One metallization line was required to form the top plate of the capacitor and another metallization line was required to form the bottom plate of a capacitor. The metallization line used for the capacitor would therefore not be available for routing signals in the particular metallization level. As such, if the integrated circuit design was designed to have dense interconnect routing, the simple implementation of a capacitor would sometimes force the addition of another metallization level to complete the required routing. This, of course, increased the size of a chip and cost of the semiconductor device. In addition, the larger a chip becomes, the more expensive it will be to package the device. Additionally, the capacitance of the capacitors used in the prior art was not that high because of the materials used for the capacitor. The prior art used standard dielectric material between the lines, as is typically done with standard interconnect structures. As a result, designers would frequently not be able to rely on these type of capacitors either because not enough capacitance was generated or because the structure became too large for the particular application. For instance, if the capacitor were too small, the function of filtering low frequency signals and/or DC signals could not be adequately accomplished.
In some cases, designers are forced to implement discrete components such as capacitors outside of the chip (i.e., on the printed circuit board) in order to complete the desired function. This also increases the cost of the resulting device.
In view of the foregoing, there is a need for a method of making capacitors in standard interconnect metallization structures. There is also a need for capacitor structures that do not occupy standard routing space on metallization levels within a semiconductor device. Additionally, there is a need for a capacitor with better performance characteristics, which can be fabricated without expensive non-standard fabrication operations.